Mentor Graphics Corp. today announced that GLOBALFOUNDRIES is helping its customers improve reliability checking by adding Calibre PERC to select 28nm bulk CMOS design enablement flows. Calibre PERC will give designers access to the new reliability verification rules developed by the IBM Semiconductor Development Alliance (ISDA), augmented with GLOBALFOUNDRIES specific checks to help prevent external latch-up. Using Calibre PERC's unique architecture, complex reliability rules that require the integration of logical (net list) and layout (GDS) information can be fully automated, eliminating manual spreadsheet-based efforts and reducing the chances of design errors. "In the past, verification of latch-up immunity depended on manual layout checks and rough approximations of device and interconnect resistance using traditional mechanisms," said Bill Liu, vice president of design enablement at GLOBALFOUNDRIES. "Now our customers can perform accurate measurements and analysis automatically using Calibre PERC's data integration capability. For example, some of our customers are currently using PERC to accurately determine the resistance of the paths in complex output driver arrays as a function of device spacing. This allows them to easily and accurately detect points in the circuit where latch-up could be an issue and to make appropriate improvements."
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